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Ordering number: EN 5650
LC865020B/16B/12B/08B
CMOS LSI
LC865020B/16B/12B/08B 8-Bit Single-Chip Microcontroller
Overview
The LC865020B/16B/12B/08B microcontrollers are 8-bit single-chip microcontrollers with the following on-chip functional blocks : * CPU : Operable at a minimum bus cycle time of 0.5 s (microsecond) * On-chip ROM capacity : Up to 20K bytes * On-chip RAM capacity : 384 bytes (LC865020B/16B/12B/08B) * 16-bit timer/counter (or two 8-bit timers) * 16-bit timer/PWM (or two 8-bit timers) * 8-channel x 8-bit A/D converter * Two 8-bit synchronous serial-interface circuits * 13-source 10-vectored interrupt system All of the functions above are fabricated on a single chip.
Package Dimensions
unit : mm
3071-DIP64S
[LC865020B/16B/12B/08B]
64 33
19.5
16.8
1
57.2
32
5.0max
4.0
0.95
0.48
1.78
1.01
SANYO : DIP64S unit : mm
3159-QFP64E
[LC865020B/16B/12B/08B]
17.2
14.0
1.6 1.0
33 32
1.6
1.0
48
49
0.15
3.0max
(1) Read-Only Memory (ROM) LC865020B 20480 x 8 LC865016B 16384 x 8 LC865012B 12288 x 8 LC865008B 8192 x 8
: bits bits bits bits
17.2 14.0
1.0
Features
1.0
64 1 17 16
0.8
0.8
0.35
0.1 2.7
15.6
0.8
SANYO : QFP64E
(2) Random Access Memory (RAM) : LC865020B/16B/12B/08B 384 x 8 bits
unit : mm
3190-SQFP64
[LC865020B/16B/12B/08B]
12.0 10.0 1.25
48 49
0.5
0.18
1.25
33 32
0.15
12.0 10.0
0.5
1.25
64
17 1 16
0.1
1.7max
1.25
0.5
0.5
SANYO : SQFP64
SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep. O3097HA (II) No. 5650-1/21
0.51min
3.2
0.25
LC865020B/16B/12B/08B
(3) Bus cycle time / Instruction cycle time The LC865020B/16B/12B/08B microcontrollers are constructed to read ROM twice within one instruction cycle. This results in 1.7 times better performance within the same instruction cycle compared to our 4-bit microcontrollers (the LC66000 series). Bus cycle time indicates the speed to read ROM.
Bus cycle time 0.5 s 2 s 7.5 s 183 s Cycle time 1 s 4 s 15 s 366 s System clock oscillation Ceramic resonator Ceramic resonator RC oscillator Crystal oscillator Oscillation frequency 12 MHz 3 MHz 800 kHz 32.768 kHz Supply voltage 4.5 to 6.0V 2.7 to 6.0V 2.7 to 6.0V 2.7 to 6.0V
(4) Ports - Input/output ports : 6 ports (42 pins) Input/output port programmable in nibble units : 1 port (8 pins) (However, when N-channel open-drain output is selected, bit-unit input is possible.) Input/output port each bit programmable : 5 ports (34 pins) Include 15 V withstand N-channel open drain output port : 3 ports (18 pins) - Input ports : 2 ports (13 pins) (5) A/D converter - 8-channel x 8-bit A/D converter (6) Serial-interface - Two 8-bit serial-interface circuits LSB first / MSB first functions switchable - Internal 8-bit band-rate generator in common with two serial-interface circuits (7) Timer - Timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is fixed to tCYC. (tCYC : cycle time) - Timer 1 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9 to 16 bits) In Mode 0 and Mode1, the resolution of Timer and PWM is fixed to tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM can be programmed to be tCYC or 1/2 tCYC - Base timer Every 500 ms overflow system for clock applications (using 32.768 kHz crystal oscillator for Base timer clock) Every 976 s, 3.9 ms, 15.6 ms, 62.5 ms overflow system (using 32.768 kHz crystal oscillator for Base timer clock) - Base timer clock selectable 32.768 kHz crystal oscillator, system clock, and programmable prescaler output of Timer 0
No. 5650-2/21
LC865020B/16B/12B/08B
(8) Buzzer output - The buzzer sound frequency is selectable ; 4 kHz, 2 kHz (using 32.768 kHz crystal oscillator for base timer clock) (9) Remote-controlled receiver circuit (shares P73/INT3/T0IN pin) - Noise rejection function - Polarity switching (10) Watchdog timer - RC external watchdog timer - Watchdog timer operation can be selected : Interrupt/reset (11) Interrupt system - 13-source 10-vectored interrupts : 1. External interrupt INT0 (including watchdog timer) 2. External interrupt INT1 3. External interrupt INT2, Timer/counter T0L (lower 8 bits) 4. External interrupt INT3, base timer 5. Timer/counter T0H (upper 8-bits) 6. Timer T1L, timer T1H 7. Serial-interface SIO0 8. Serial-interface SIO1 9. A/D converter 10. Port 0 - Built-in interrupt priority control register Microcontroller supports 3 levels of multiple interrupt; low level, high level, and highest level. For the 11 interrupt requests from INT2 through Port 0, high/low level interrupt priority can be specified using the priority control register. Also, for INT0 and INT1, highest/low level interrupt priority can be specified. (12) Real-time service operation Synchronizing with the interrupt request signals, the real-time service starts a 4-byte data transfer between which special function registers within 1-instruction cycle after the request signal occurs, and then completes its operation within 5-instruction cycles. This operation is performed in parallel with CPU operation.
(13) Subroutine stack - 128 levels (Max.) : The stack is located in RAM. (14) Multiplication and division 16 bits x 8 bits (7-instruction cycles) 16 bits / 8 bits (7-instruction cycles)
(15) 3 oscillation circuits - On-chip RC oscillator circuit for the system clock - On-chip CF oscillator circuit for the system clock - On-chip crystal oscillator circuit for the system clock and the time-base clock XT1 pin can be used as P74.
No. 5650-3/21
LC865020B/16B/12B/08B
(16) Standby function - HALT mode HALT mode is used to reduce power dissipation. In this mode, program execution is stopped. This mode can be released by an interrupt request signal or initial system reset request signal. - HOLD mode The HOLD mode is used to stop all oscillators RC (internal), CR and Crystal. This mode can be released by the following operations * Set Low level to Reset pin (RES). * Set predefined level to P70/INT0, P71/INT1 pins (programmable). * Set Low level to Port 0 pin/pins (programmable). (17) Factory shipment * DIP64S , QFP64E , SQFP64 delivery form (18) Development support tools Evaluation (EVA) chip : EPROM version : One time ROM version : Emulator :
LC866098 LC86E5032 LC86P5032 EVA-86000 + ECB866600 (Evaluation chip board) + POD865000 (POD for DIP64S) + POD865010 (POD for QFP64E)
No. 5650-4/21
LC865020B/16B/12B/08B
Pin Assignments
DIP64S
P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM TEST1 RES XT1/P74 XT2 VSS VSS CF1 CF2 VDD VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P07 P06 P05 P04 P03 P02 P01 P00 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VDDVPP VSS VSS P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34
Top view
No. 5650-5/21
LC865020B/16B/12B/08B
P14/SI1/SB1
P11/SI0/SB0
QFP64E
P16/BUZ P15/SCK1 P17/PWM
P13/SO1 P12/SCK0
P10/SO0 P07
P06
P05 P04
P03
P02 P01
48
P00
32
47 46 45 42 41 40 39 38 37 36 35
TEST1 RES XT1/P74 XT2 VSS VSS CF1 CF2 VDD VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 64
34 33
44
43
49 50 51 52 53 54 55 56 57 58 59 60 61 62
P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VDDVPP VSS VSS P51 P50 P47 P46 P45 P44
16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
11 12 P36 P37
13
P30
P31
P32
P33 P34
P35
P40 P41
P42
14 15
63
10 1 2 3 4 5 6 7 8 9
P70/INT0
P71/INT1
P72/INT2/T0IN P73/INT3/T0IN
P43
Top view
SQFP64
P17/PWM 48
P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P07 P06 P05 P04 P03 P02 P01 P00 47 46 45 44 43 42 41 40 37 36 35 34 39 38 33
32 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VDDVPP VSS VSS P51 P50 P47 P46 P45 P44
16
TEST1 RES XT1/P74 XT2 VSS VSS CF1 CF2 VDD VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 64
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43
12 13 14 15
1 2 3 4 5 6 7 8 9 10 11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Top view
No. 5650-6/21
LC865020B/16B/12B/08B
System Block Diagram
IR Interrupt control Stand-by control ROM
PLA
CF RC X tal Clock generator
Bus
PC
ACC Base timer SIO0 SIO1 Timer 0 Timer 1 ADC INT0 to 3 Noise rejection filter Real time service Bus Bus interface Port1 Port7 Port8 ALU Port2 Port3 Port4 PSW Port5 RAR RAM RAM (128 bytes) B register C register
Stack pointer
PORT 0 Watchdog timer
No. 5650-7/21
LC865020B/16B/12B/08B
LC865020B/16B/12B/08B Pin Description
Pin name VSS VDD VDDVPP* PORT0 P00 to P07 I/O I/O Function description Power supply (-) Power supply (+) Power supply (+) * * * * 8-bit input/output port Input for port 0 interrupt Data direction programmable in nibble units Input for HOLD release * Pull-up resistor : Present / Not present * Output form : CMOS/N-channel open-drain * Output form : CMOS/N-channel open-drain Option
PORT1 P10 to P17
I/O
* 8-bit input/output port * Data direction can be specified for each bit. * Other pin functions P10 SIO0 data output P11 SIO0 data input /bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input /bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer1 output (PWM output) * 8-bit input/output port * Input/output in bit units * 8-bit input/output port * Input/output in bit units * 15 V withstand at N-channel open-drain output * 8-bit input/output port * Input/output in bit units * 15 V withstand at N-channel open-drain output * 2-bit input/output port * Input/output in bit units * 15 V withstand at N-channel open-drain output
PORT2 P20 to P27 PORT3 P30 to P37
I/O I/O
Output form : CMOS/N-channel open-drain * Pull-up resistor : Present / Not present * Output form : CMOS/N-channel open-drain * Pull-up resistor : Present / Not present * Output form : CMOS/N-channel open-drain * Pull-up resistor : Present / Not present * Output form : CMOS/N-channel open-drain
PORT4 P40 to P47
I/O
PORT5 P50 , P51
I/O
* Connect as in the following figure to reduce noise into VDD. Short-circuit the VDD terminal to the VDDVPP pin. Short-circuit the two VSS pins.
LSI
V DD VDD
V DDV PP VDDVPP V SS VSS VSS VSS
No. 5650-8/21
LC865020B/16B/12B/08B
Pin name PORT7 P70 P71 to P74 I/O I I/O Function description * 5-bit input port * Other pin functions P70: INT0 input / HOLD release / N-channel Tr. output for watchdog timer P71: INT1 input / HOLD release input P72: INT2 input / timer 0 event input P73: INT3 input with noise filter/timer 0 event input P74: XT1 input pin for 32.768 kHz crystal oscillator * Interrupt received form, vector address Rising Falling Rising & falling INT0 INT1 INT2 INT3 PORT8 P80 to P87 RES TEST1 I High level Low level Option Pull-up resistor : Present / Not present (P70,71,72,73) * P74 does not have pull-up resistor option.
Vector
Enable Enable Disable Enable Enable Enable Enable Disable Enable Enable Enable Enable Enable Disable Disable Enable Enable Enable Disable Disable
03H 0BH 13H 1BH
* 8-bit input port * Other function AD input port (8 port pins) Reset pin with pull-up resistor * Test pin Should be left open. * Output fixed HIGH * Input pin for 32.768 kHz crystal oscillator * Other function Input port P74 When not in use, connect to VDD . Output pin for 32.768 kHz crystal oscillator When not in use, should be left open. Input pin for ceramic resonator oscillator Output pin for ceramic resonator oscillator
I O
XT1/P74
I
XT2 CF1 CF2
O I O
* All port options can be specified for each bit. * State of pins at reset
Pin name Port 0 Ports 70, 71, 72, 73 Ports 1, 2 Ports 3, 4, 5 Input/output mode Input Input State of pull-up resistor specified at pull-up option Fixed pull-up resistor exist Programmable pull-up resistor OFF
No. 5650-9/21
LC865020B/16B/12B/08B
Specifications
1. Absolute Maximum Ratings at Ta = 25C , VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Supply voltage Input voltage VDD max VI(1) VDD, VDDVPP * Ports 71, 72, 73, 74 * Port 8 * RES * Ports 0, 1, 2 * Ports 3, 4, 5 at CMOS output option Ports 3, 4, 5 at N-ch open-drain output option Ports 0, 1, 2, 3, 4, 5 CMOS output at each pin Total of all pins Total of all pins At each pin At each pin Total of all pins Total of all pins Total of all pins Ta = -30 to +70C Ta = -30 to +70C Ta = -30 to +70C -30 VDD = VDDVPP min -0.3 -0.3 Ratings typ max +7.0 VDD+0.3 V Unit
Input/output voltage
VIO(1)
-0.3
VDD+0.3
VIO(2)
-0.3
+15
Highlevel output current
Peak output current Total output current Peak output current Total output current
IOPH(1)
-4
mA
IOAH(1) IOAH(2) IOPL(1) IOPL(2) IOAL(1) IOAL(2) IOAL(3)
Ports 0, 1 Ports 2, 3, 4, 5 Ports 0, 1, 2, 3, 4, 5 Port 70 Ports 0, 1 Port 70 Port 2 Ports 3, 4, 5 DIP64S QFP64E SQFP64
-20 -20 20 15 40 40 80 700 420 290 +70 C mW
Lowlevel output current
Power dissipation (max.)
Pd max (1) Pd max (2) Pd max (3)
Operating temperature range Storage temperature range
Topr
Tstg
-65
+150
No. 5650-10/21
LC865020B/16B/12B/08B
2. Recommended Operating Ranges at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Operating voltage range VDD(1) VDD(2) HOLD voltage VHD VDD VDD 0.98 s tCYC tCYC 400 s 3.9 s tCYC tCYC 400 s RAM and Registers hold voltage at HOLD mode. Output disable Output disable 2.7 to 6.0 2.7 to 6.0 min 4.5 2.7 2.0 Ratings typ max 6.0 6.0 6.0 V Unit
Input high voltage
VIH(1) VIH(2)
Port 0 (Schmitt) * Ports 1, 2 * Ports 72, 73 (Schmitt) * Port 70 Port input/interrupt * Port 71 * RES (Schmitt) Port 70 Watchdog timer * Port 74 * Port 8 Ports 3, 4, 5 of CMOS output (Schmitt) Ports 3, 4, 5 of opendrain output (Schmitt) Port 0 (Schmitt) * Ports 1, 2, 3, 4, 5 * Ports 72, 73 (Schmitt) * Port 70 Port input/interrupt * Port 71 * RES (Schmitt) Port 70 Watchdog timer * Port 74 * Port 8
0.4VDD +0.9 0.75VDD
VDD VDD
VIH(3)
Output N-channel transistor OFF
2.7 to 6.0
0.75VDD
VDD
VIH(4) VIH(5) VIH(6)
Output N-channel transistor OFF Output N-channel transistor OFF Output disable
2.7 to 6.0 27 to 6.0 4.0 to 6.0 2.7 to 4.0
0.9VDD 0.75VDD 0.75VDD 0.8VDD 0.75VDD 0.8VDD VSS VSS
VDD VDD VDD VDD 13.5 13.5 0.2VDD 0.25V DD
VIH(7)
Output disable
4.0 to 6.0 2.7 to 4.0
Input low voltage
VIL (1) VIL (2)
Output disable Output disable
2.7 to 6.0 2.7 to 6.0
VIL(3)
N-channel transistor OFF
2.7 to 6.0
VSS
0.25VDD
VIL(4) VIL(5) Operating cycle time tCYC
N-channel transistor OFF Output N-channel transistor OFF
2.7 to 6.0 2.7 to 6.0 4.5 to 6.0 2.7 to 6.0
VSS VSS 0.98 3.9
0.8VDD -1.0 0.25VDD 400 400 s
No. 5650-11/21
LC865020B/16B/12B/08B
Parameter Symbol Pins Conditions VDD[V] Oscillation frequency range (Note 1) FmCF(1) CF1, CF2 * 12 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 1. * 3 MHz (ceramic 2.7 to 6.0 resonator oscillation). * Refer to Figure 1. RC oscillation XT1, XT2 * 32.768 kHz (crystal oscillation). * Refer to Figure 2. 2.7 to 6.0 2.7 to 6.0 min 11.76 Ratings typ 12 max 12.24 MHz Unit
FmCF(2)
CF1, CF2
2.94
3
3.06
FmRC FsXtal
0.4
0.8 32.768
3.0 kHz
Oscillation stable time period (Note 1)
tmsCF(1)
CF1, CF2
* 12 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 3. * 3 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 3. 2.7 to 6.0 * 32.768 kHz (crystal oscillation). * Refer to Figure 3. 4.5 to 6.0 2.7 to 6.0
0.03
0.5
ms
tmsCF(2)
CF1, CF2
0.2 0.2 1 1
2 6 1.5 3 s
tssXtal
XT1, XT2
(Note 1) Refer to Table 1 and Table 2 for oscillation constant.
No. 5650-12/21
LC865020B/16B/12B/08B
3. Electrical Characteristics at Ta = -30C to +70C , VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Input high current IIH(1) Ports 3, 4, 5 of opendrain output * Output disabled * VIN = 13.5 V (including off-state leak current of the output transistor) * Output disabled * Pull-up MOS transistor OFF. VIN = V DD (including off-state leak current of the output transistor) VIN = VDD 2.7 to 6.0 min Ratings typ max 5 A Unit
IIH(2)
* Port 0 without pull-up MOS transistor * Ports 1, 2, 3, 4, 5
2.7 to 6.0
1
IIH(3)
* Ports 70, 71, 72, 73 without pull-up MOS transistor * Port 8 RES * Ports 1, 2, 3, 4, 5 * Port 0 without pull-up MOS transistor
2.7 to 6.0
1
IIH(4) Input low current I IL (1)
VIN = VDD * Output disabled * Pull-up MOS transistor OFF. VIN = VSS (including off-state leak current of the output transistor) VIN = VSS
2.7 to 6.0 2.7 to 6.0 -1
1
IIL(2)
* Ports 70, 71, 72, 73 without pull-up MOS transistor * Port 8 RES Ports 1, 2, 3, 4, 5 of CMOS output Ports 1, 2, 3, 4, 5
2.7 to 6.0
-1
IIL(3) Output high voltage Output low voltage VOH(1) VOH(2) VOL(1) VOL(2) VOL(3)
VIN = VSS IOH = -1 mA IOH = -0.1 mA IOL = 10 mA IOL = 1.6 mA * IOL = 1.0 mA * The current of any unmeasured pin is 1 mA or less.
2.7 to 6.0 4.5 to 6.0 2.7 to 6.0 4.5 to 6.0 4.5 to 6.0 2.7 to 6.0
-1 VDD-1 VDD-0.5 1.5 0.4 0.4 V
VOL(4) VOL(5) Pull-up MOS transistor resistor Hysteresis voltage Rpu VHIS
Port 70
IOL = 1 mA IOL = 0.5 mA
4.5 to 6.0 2.7 to 6.0 4.5 to 6.0 2.7 to 4.5 2.7 to 6.0 15 25 40 70 0.1VDD
0.4 0.4 70 150 k V
* Ports 1, 2, 3, 4, 5 * Ports 70, 71, 72, 73 * Ports 1, 2, 3, 4, 5 * Ports 70, 71, 72, 73 * RES All pins
VOH = 0.9 VDD Output disable
Pin capacitance
CP
* f = 1 MHz Unmeasured input pins are set to VSS level. * Ta = 25C
2.7 to 6.0
10
pF
No. 5650-13/21
LC865020B/16B/12B/08B
4. Serial Input/Output Characteristics at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Cycle Lowlevel pulse width Highlevel pulse width Cycle tCKCY(1) tCKL(1) SCK0, SCK1 Refer to Figure 5. 2.7 to 6.0 2.7 to 6.0 min 2 1 Ratings typ max tCYC Unit
Input clock
tCKH(1)
2.7 to 6.0
1
Serial clock
tCKCY(2)
SCK0, SCK1
* Use an external pull-up resistor (1 k) with opendrain output. * Refer to Figure 5.
2.7 to 6.0
2
Output clock
Lowlevel pulse width Highlevel pulse width
tCKL(2)
2.7 to 6.0
1/2tCKCY
tCKH(2)
2.7 to 6.0
1/2tCKCY
Serial input
Data setup time Data hold time Output delay time (Serial clock is extrnal clock.) Output delay time (Serial clock is internal clock.)
tICK tCKI tCKO(1)
* SI0, SI1 * SB0, SB1
* Set to the rise of SCK0, SCK1. * Refer to Figure 5.
4.5 to 6.0 2.7 to 6.0 4.5 to 6.0 2.7 to 6.0 4.5 to 6.0
0.1 0.4 0.1 0.4 7/12tCYC +0.2 7/12tCYC +1 1/3tCYC +0.2 1/3tCYC +1
s
* SO0, SO1 * SB0, SB1
* Use an external pull-up resistor (1 k) with opendrain output. * Set to the fall of SCK0, SCK1. * Refer to Figure 5.
2.7 to 6.0 4.5 to 6.0 2.7 to 6.0
Serial output
tCKO(2)
No. 5650-14/21
LC865020B/16B/12B/08B
5. Pulse Input Conditions at Ta = -30C to +70C , VSS = 0 V
Parameter
Symbol
Pins
Conditions VDD[V] min 1
Ratings typ max
Unit
High/low-level pulse width
tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4)
* INT0, INT1 * INT2/T0IN * INT3 INT3/T0IN (Noise rejection filter time constant is 1/1.) INT3/T0IN (Noise rejection filter time constant is 1/16.) RES
* Interrupt acceptable * Timer/counter 0 pulse countable Interrupt acceptable
2.7 to 6.0
tCYC
2.7 to 6.0
2
Interrupt acceptable
2.7 to 6.0
32
Reset acceptable
2.7 to 6.0
200
s
6. A/D Converter Characteristics at Ta = -30C to +70C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Resolution Absolute precision Conversion time N ET (Note 2) tCAD A/D conversion time = 16 x tCYC (ADCR2 = 0) (Note 3) A/D conversion time = 32 x tCYC (ADCR2 = 1) (Note 3) Analog input voltage range Analog port input current VAIN IAINH IAINL AN0 to AN7 VAIN = VDD VAIN = VSS 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 15.68 (tCYC = 0.98 s) 31.36 (tCYC = 0.98 s) VSS 65.28 (tCYC = 4.08 s) 130.56 (tCYC = 4.08 s) VDD +1 -1 V A s 4.5 to 6.0 4.5 to 6.0 min Ratings typ 8 1.5 max bit LSB Unit
(Note 2) (Note 3)
Quantizing error (1/2 LSB) is not included. Conversion time is the period from execution of instruction starting the conversion to completion of shifting the A/D converted value to the register.
No. 5650-15/21
LC865020B/16B/12B/08B
7. Current Drain Characteristics at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Current drain during basic operation (Note 4) IDDOP(1) VDD * FmCF = 12 MHz 4.5 to 6.0 for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator * Internal RC oscillator stopped. * FmCF = 3 MHz 4.5 to 6.0 for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator * Internal RC oscillator stopped. 2.7 to 4.5 * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : RC oscillator * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 32.768 kHz * Internal RC oscillator stopped. 4.5 to 6.0 min Ratings typ 10 max 20 mA Unit
IDDOP(2)
3
7
IDDOP(3) IDDOP(4)
1.5 0.7
5 3.0
IDDOP(5) IDDOP(6)
2.7 to 4.5 4.5 to 6.0
0.4 35
2.5 100 A
IDDOP(7)
2.7 to 4.5
15
50
No. 5650-16/21
LC865020B/16B/12B/08B
Parameter Symbol Pins Conditions VDD[V] Current drain at HALT mode (Note 4) IDDHALT(1) VDD * HALT mode 4.5 to 6.0 * FmCF = 12 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillatior. * System clock : CF oscillator. * Internal RC oscillator stopped. * HALT mode 4.5 to 6.0 FmCF = 3 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : CF oscillator. * Internal RC oscillator stopped. 2.7 to 4.5 * HALT mode FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : RC oscillator * HALT mode FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 32.768 kHz * Internal RC oscillator stopped. VDD HOLD mode 4.5 to 6.0 min Ratings typ 5 max 10 mA Unit
IDDHALT(2)
2.2
4.6
IDDHALT(3) IDDHALT(4)
0.8 400
2.5 1000 A
I DDHALT (5) I DDHALT (6)
2.7 to 4.5 4.5 to 6.0
200 25
750 100
I DDHALT (7) Current drain at HOLD mode (Note 4) I DDHOLD(1) I DDHOLD(2)
2.7 to 4.5 4.5 to 6.0 2.7 to 4.5
8 0.05 0.02
40 30 20
(Note 4) The currents to output transistors and pull-up MOS transistors are ignored.
No. 5650-17/21
LC865020B/16B/12B/08B
Oscillation type 12 MHz ceramic resonator oscillation Supplier Murata Oscillator CSA12.0MTZ CST12.0MTW Kyocera 3 MHz ceramic resonator oscillation Murata KBR-12.0M CSA3.00MG040 CST3.00MGW040 Kyocera KBR-3.0MS 47 pF 33 pF 100 pF On chip 47 pF C1 33 pF On chip 33 pF 100 pF C2 33 pF
* K rank (10%) and SL characteristics must be used for C1 and C2. Table 1. Ceramic Resonator Oscillation Guaranteed Constants (Main clock)
Oscillation type 32.768 kHz crystal oscillation
Supplier Kyocera
Oscillator KF-38G-13P0200
C3 18 pF
C4 18 pF
* J rank (5%) and CH characteristics must be used for C3 and C4. (For applications which do not need high precision, use K rank (10%) and SL characteristics.) Table 2. Crystal Oscillation Guaranteed Constants (Sub-clock) Notes * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillator pins as possible with the shortest pattern length. * If other oscillators are used, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
C1
CF
C2
C3
X tal
C4
Main-clock circuit Figure 1 Ceramic Resonator Oscillator
Sub-clock circuit Figure 2 Crystal Oscillator
No. 5650-18/21
LC865020B/16B/12B/08B
VDD VDD lower limit 0V Reset time
Power supply
RES
Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode

HOLD release signal Internal RC resonator oscillation
Valid
tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode
HOLD
Instruction execution mode

Figure 3 Oscillation Stable Time
VDD VDD RRES RES CRES
Values of the and R of CRES, RRES that (Note) Fix CRESvalue RES should be set such is that reset time is at least 200 after Power supply sure to reset untill 200s, s, measured from the over inferior limit of supply voltage. has been point when VDD exceeds VDD lower limit.
Figure 4 Reset Circuit No. 5650-19/21
LC865020B/16B/12B/08B
0.5VDD 0.5VDD < AC timing point >
tCKCY tCKL
SCK0 SCK1
VDD VDD
tCKH 1k tICK tCKI
SI0 SI1
tCKO
SO0,SO1 SB0,SB1
50pF
< Timing >
< Test load >
Figure 5 Serial Input/Output Test Conditions
tPIL
tPIH
Figure 6 Pulse Input Timing Conditions
No. 5650-20/21
LC865020B/16B/12B/08B
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1997. Specifications and information herein are subject to change without notice.
No. 5650-21/21

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